【電磁技術在線】【EDA篇】- 5. 高速信道
講師：Longfei Bai
00：00 內容介紹
03：40 part1：模型介紹
05：40 part2：無源高速互聯S參數
11：00 part3：Tran-Co流程介紹
15：25 macromodeling 宏建模（HSPICE，IDEM）
20：00 part4：前向糾錯FEC （階梯響應，抖動DJ&RJ，DFE，誤差傳播，馬爾可夫鏈， Reed Solomon編碼）
35：50 part5: IBIS AMI
We simulate a 1 meter backplane with a baud rate of 28 Gsym/s and PAM4 modulation. DFE (Decision Feedback Equalizer)and FFE (Feed Forward Equalizer) are used to reach a BER of 3.5e-5. Error propagation caused by DFE is modeled by Markov Chain. FEC analysis is performed and it shows that RS10 (528, 514, 7) can improve the BER (Bit ErrorRate) further to 6.4e-14.
For the simulation of the step response, a new transient co-simulation (tran-co) workflow is presented. In comparison to traditional workflows, it requires less manual work and simulation time. Its accuracy is validated by comparing to traditional workflows.
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T-Solver: State-of-the-art 3D time domain solver based on Finite Integral Technique.
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GPUAcceleration: Common GPU series supported, especially for T-solver.
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Design Environment: Tran-Co (together with T-solver) & Circuit workflow and IBIS AMI [3].
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IDEM: State-of-the-art Macro Modelling tool.
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EyeDiagramTool: Eye diagram analysis tool. Statistical Eye, Equalizations and PAM4.
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VBA Interface: Process simulation results flexibly. FEC analysis.
References:
[1] R. Narasimha, N. Warke and N.Shanbhag, “Impact of DFE ErrorPropagation on FEC-Based
High-Speed I/O Links” in IEEEGLOBECOM, 2009
[2] Y. Yu, T. Guo and S. Zhu, “A Way to Evaluate post-FEC BER based onIBIS-AMI Model” in Asian
IBIS Summit,2017
[3] IBIS OpenForum.https://ibis.org/
[4] Synopsys Inc.https://www.synopsys.com/
[5] X. Dong and C. Huang, “Necessity for integrating FEC functionality forPAM4 in AMI simulations”
in Asian IBIS Summit, 2016
