CST2017最新版和SP1發(fā)布啦

來源：更新時(shí)間：2024-08-11 閱讀：

不知道最新版本有啥新特色

來學(xué)習(xí)一下

不知道哪里能下載啊

CST 2017幫助文件《What's New in this Version》：
CST STUDIO SUITE
- Automatic download of update packages on Linux
- Linux installation is pure 64-bit
- New 3D Component Library
- Solid annotations including images
- Wire to Solid conversion
- Interactive Boolean Operation with multiple objects
- Enhanced STEP Export (Hierarchical Tree, etc)
- New options in 3D Postprocessing Ribbon
- Ability to store 3D-Plots with all settings (incl.copy/paste)
- Parametric farfield cuts without result template
- Touchstone 2.0 - support of multiple reference impedances
- Meshing:
* Manual fixpoints in hexahedral mesh engine
* Extended meshing feedback in Message window and Navigation Tree
High Frequency Simulation
- Visualization of discretized wire endpoint connectivity (incl lumped elements and discrete ports) (T)
- Surface Roughness Setting for Lossy Metal (T)
- Off-axis anisotropic solid material (T-TLM)
- Support for voxel import (T-TLM)
- Load spice net list as lumped element (F)
- Biased ferrite workflow now in SAM (F)
- Temperature dependent materials (F)
- Tabulated Surface Impedance material (I)
- Current visualization on wires (I)
- Antenna to Antenna Coupling (NFS+FFS) (A)
Low Frequency Simulation
- Time Periodic Steady State Solver (LT-MQS)
- New Electrical Machine SAM Workflow
- Nonlinear permanent magnet characteristics (MS)
- Improved Coil-Group handling
Particle Simulation
- New emission model for plasma ion sources (TRK)
- More robust particle monitors (TRK)
- Volume ionization in PIC solver (PIC)
- Multi GPU support (PIC)
- External Field Improvements (TRK/PIC)
- Performance improvement for low beta beams (WAK)

Cable Simulation
- Workflow Improvements for models with many pins
- The real thickness of cable segments can now be visualized
- RLCG values per unit length now available in the impedance calculator
- Improved twisted cable model
- Multiple drain wires now supported
Circuit Simulation
- Interference Task
- Linux support for batch processing
- New IBIS infrastructure (incl. reference block)
- New Parameter Tuner UI
- PSpice Export
PCB Simulation
- Multiple power supplies for IR Drop
- Voltage regulators for IR Drop to model different voltage levels in one setup
- Part Library supports IO devices and composite devices
- Layer Stackup cross section view
- DC-point extraction for 3DFEFD
Boardcheck
- Improved rule names and labels
- Improved structure of violation output
EDA Import
- Layer stackup representation in navigation tree group
- Materials from CST library can be assigned to Stackup in EDA import dialog
- Added GUI for port impedance definition
- Automatic creation of current and voltage ports for LF simulations
Chip Interface
- Support of net selection
- Support of derived layers (AND, NOT, ect…)
- Clean 3D geometry creation
- Built-in PDK for testing
Thermal Simulation
- New CHT Solver, solving all modes of heat transfer, including conduction, convection and radiation
- Support of Moving media in TET-Solvers (THs, THt)
- Import of loss distributions in sub-volumes